This disclosure relates to a solid-state image pickup device and a method for manufacturing same, and also to an image pickup apparatus provided with the solid-state image pickup device.
In solid-state image pickup devices, in order to make up for reduction in charge storage capacitance ascribed to the miniaturization of pixels being advanced, it has been proposed to additionally form, aside from a charge storage region of an existing sensor unit, an impurity region of the same conduction type as the charge storage region therebelow.
Further, there has been proposed a charge storage unit wherein ions having different energies are injected plural times into below a charge storage region to form a plurality of impurity regions, followed by combination with a known charge storage region (see, for example, Japanese Patent Laid-open No. 2002-164529).
In this Patent Application, a CCD (charge-coupled device) solid-state image pickup device is described. With respect to a CMOS (complementary metal-oxide semiconductor) solid-state image pickup device, a plurality of impurity regions may be likewise formed beneath a storage image pickup region of a sensor unit thereby configuring a charge storage unit.
A schematic configuration view (sectional view) of the CMOS solid-state image pickup device configured in this way is shown in FIGS. 5A and 5B. FIG. 5A is a sectional view at a face orthogonal to a transfer gate and 5B is a sectional view, taken along line X-X′ of FIG. 5A.
It will be noted that although a first charge storage unit and a second charge storage unit are mentioned in the Laid-open Patent Application No. 2002-164529, the hitherto known charge storage region is called herein main charge storage region and the lower impurity region is called charge storage sub-region.
The solid-state image pickup device shown in FIGS. 5A and 5B is configured such that individual pixels are isolated with a P+ device isolation region 53, and a photodiode (PD) of a sensor unit and a charge transfer portion are formed at the inside isolated with the device isolation region 53. In the figures, indicated by 51 is a semiconductor substrate (i.e. a semiconductor substrate or a semiconductor substrate and a semiconductor epitaxial layer formed thereon) and by 52 is a p−semiconductor well region formed as buried in the semiconductor substrate 51. An overflow barrier is formed by the semiconductor well region 52.
In this solid-state image pickup device, an n-type charge storage sub-region is formed particularly beneath an n+-type charge storage region 54 of a sensor unit. The charge storage sub-region is constituted of three n-type impurity regions including a first charge storage sub-region 61, a second charge storage sub-region 62 and a third charge storage sub-region 63 as viewed from below.
The charge storage sub-region formed of the first charge storage sub-region 61, second charge storage sub-region 62 and third charge storage sub-region 63 acts to increase a charge storage capacitance over the case where the charge storage region 54 alone is deeply formed.
In this way, it becomes possible to make up for the reduction of a charge storage capacitance when pixels are miniaturized and to suppress sensitivity from lowering as will be caused by the miniaturization of the pixels.
Additionally, photoelectrons photoelectrically converted at a deep region of a photodiode can be efficiently transferred.
The first, second and third charge storage sub-regions 61, 62, 63 can be successively formed by n-type impurity ion injections of different energy levels.
The potential distribution diagram at the section of FIG. 5B is shown in FIG. 6.
As shown in FIG. 6, a potential distribution extended in a direction of depth is formed by the formation of the charge storage sub-regions 61, 62, 63.
When an n-type impurity is subjected to multistage cycles of ion injection to form charge storage sub-regions, such a potential along the depth can be designed.